Node / meshcore / MeshCore / files / src / helpers / radiolib / CustomSTM32WLx.h

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Tff7b72#Tff7b72pragma once

Tff7b72#Tff7b72include T8b949e<RadioLib.h>

Te6edf3class Te6edf3CustomSTM32WLx Tff7b72: Te6edf3public Te6edf3STM32WLx Tb4b4b4{

Tffa657uint32_t Te6edf3_preambleMillis Tff7b72= T79c0ff66Tb4b4b4;

Tffa657uint32_t Te6edf3_maxPayloadMillis Tff7b72= T79c0ff3934Tb4b4b4;

Tffa657uint32_t Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4;

Tffa657bool Te6edf3_headerSeen Tff7b72= Tffa657falseTb4b4b4;

Te6edf3publicTff7b72:

Te6edf3CustomSTM32WLxTb4b4b4(Te6edf3STM32WLx_Module Tff7b72*Te6edf3modTb4b4b4) Tff7b72: Te6edf3STM32WLxTb4b4b4(Te6edf3modTb4b4b4) Tb4b4b4{ Tb4b4b4}

Tffa657int16_t Te6edf3startReceiveTb4b4b4(Tb4b4b4) Te6edf3override Tb4b4b4{

T8b949e// include the PREAMBLE_DETECTED irq bit in reported flags

Tff7b72return Te6edf3STM32WLxTff7b72:Tff7b72:Te6edf3startReceiveTb4b4b4(Te6edf3RADIOLIB_SX126X_RX_TIMEOUT_INFTb4b4b4, Te6edf3RADIOLIB_IRQ_RX_DEFAULT_FLAGS Tff7b72| Tb4b4b4(T79c0ff1UL Tff7b72<Tff7b72< Te6edf3RADIOLIB_IRQ_PREAMBLE_DETECTEDTb4b4b4)Tb4b4b4, Te6edf3RADIOLIB_IRQ_RX_DEFAULT_MASKTb4b4b4, T79c0ff0Tb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657bool Te6edf3isReceivingTb4b4b4(Tb4b4b4) Tb4b4b4{

Tffa657uint32_t Te6edf3irq Tff7b72= Te6edf3getIrqFlagsTb4b4b4(Tb4b4b4)Tb4b4b4;

Tffa657bool Te6edf3preamble Tff7b72= Te6edf3irq Tff7b72& Te6edf3RADIOLIB_SX126X_IRQ_PREAMBLE_DETECTEDTb4b4b4; T8b949e// bit 2

Tffa657bool Te6edf3header Tff7b72= Te6edf3irq Tff7b72& Te6edf3RADIOLIB_SX126X_IRQ_HEADER_VALIDTb4b4b4; T8b949e// bit 4

Tffa657bool Te6edf3hdrErr Tff7b72= Te6edf3irq Tff7b72& Te6edf3RADIOLIB_SX126X_IRQ_HEADER_ERRTb4b4b4; T8b949e// bit 5

Tffa657uint32_t Te6edf3now Tff7b72= Te6edf3millisTb4b4b4(Tb4b4b4)Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3hdrErrTb4b4b4) Tb4b4b4{

Te6edf3clearIrqFlagsTb4b4b4(Te6edf3RADIOLIB_SX126X_IRQ_PREAMBLE_DETECTED Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_HEADER_VALID Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_HEADER_ERR Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_SYNC_WORD_VALIDTb4b4b4)Tb4b4b4;

Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3_headerSeen Tff7b72= Tffa657falseTb4b4b4;

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3header Tff7b72&Tff7b72& Te6edf3_headerSeenTb4b4b4) Tb4b4b4{

T8b949e// something cleared the header flag, reset our state.

Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4; Te6edf3_headerSeen Tff7b72= Tffa657falseTb4b4b4;

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3headerTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Tff7b72!Te6edf3_headerSeenTb4b4b4) Tb4b4b4{ Te6edf3_headerSeen Tff7b72= Tffa657trueTb4b4b4; Te6edf3_activityAt Tff7b72= Te6edf3nowTb4b4b4; Tb4b4b4}Tb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3_activityAt Tff7b72> Te6edf3_maxPayloadMillisTb4b4b4) Tb4b4b4{

Te6edf3MESH_DEBUG_PRINTLNTb4b4b4(Ta5d6ff"Ta5d6ffClearing header IRQ after %umsTa5d6ff"Tb4b4b4, Te6edf3_maxPayloadMillisTb4b4b4)Tb4b4b4;

Te6edf3clearIrqFlagsTb4b4b4(Te6edf3RADIOLIB_SX126X_IRQ_PREAMBLE_DETECTED Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_HEADER_VALID Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_HEADER_ERR Tff7b72| Te6edf3RADIOLIB_SX126X_IRQ_SYNC_WORD_VALIDTb4b4b4)Tb4b4b4;

Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4; Te6edf3_headerSeen Tff7b72= Tffa657falseTb4b4b4;

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Tff7b72return Tffa657trueTb4b4b4;

Tb4b4b4}

Tff7b72if Tb4b4b4(Te6edf3preambleTb4b4b4) Tb4b4b4{

Tff7b72if Tb4b4b4(Te6edf3_activityAt Tff7b72=Tff7b72= T79c0ff0Tb4b4b4) Te6edf3_activityAt Tff7b72= Te6edf3nowTb4b4b4;

Tff7b72if Tb4b4b4(Te6edf3now Tff7b72- Te6edf3_activityAt Tff7b72> Te6edf3_preambleMillisTb4b4b4) Tb4b4b4{

Te6edf3clearIrqFlagsTb4b4b4(Te6edf3RADIOLIB_SX126X_IRQ_PREAMBLE_DETECTEDTb4b4b4)Tb4b4b4;

Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4;

Te6edf3MESH_DEBUG_PRINTLNTb4b4b4(Ta5d6ff"Ta5d6ffClearing preamble IRQ after %umsTa5d6ff"Tb4b4b4, Te6edf3_preambleMillisTb4b4b4)Tb4b4b4;

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Tff7b72return Tffa657trueTb4b4b4;

Tb4b4b4}

Te6edf3_activityAt Tff7b72= T79c0ff0Tb4b4b4; Te6edf3_headerSeen Tff7b72= Tffa657falseTb4b4b4;

Tff7b72return Tffa657falseTb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3setPreambleMillisTb4b4b4(Tffa657uint32_t Te6edf3preambleMillisTb4b4b4) Tb4b4b4{

Te6edf3_preambleMillis Tff7b72= Te6edf3preambleMillisTb4b4b4;

Te6edf3MESH_DEBUG_PRINTLNTb4b4b4(Ta5d6ff"Ta5d6ffSet _preambleMillis=%uTa5d6ff"Tb4b4b4, Te6edf3_preambleMillisTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tffa657void Te6edf3setMaxPayloadMillisTb4b4b4(Tffa657uint32_t Te6edf3payloadMillisTb4b4b4) Tb4b4b4{

Te6edf3_maxPayloadMillis Tff7b72= Te6edf3payloadMillisTb4b4b4;

Te6edf3MESH_DEBUG_PRINTLNTb4b4b4(Ta5d6ff"Ta5d6ffSet _maxPayloadMillis=%uTa5d6ff"Tb4b4b4, Te6edf3_maxPayloadMillisTb4b4b4)Tb4b4b4;

Tb4b4b4}

Tb4b4b4}Tb4b4b4;